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Executive Insight Corner

Inside 1α — the World’s Most Advanced DRAM Process Technology

By Thy Tran - 2021-01-25

Micron recently announced that we’re shipping memory chips built using the world’s most advanced DRAM process technology. That process is, cryptically, called “1α” (1-alpha). What does that mean and just how amazing is it?

The history of chipmaking is all about shrinking the circuits to fit more transistors or memory cells on a chip. Sixty years ago, the first chips had components — transistors and such — that you could see with the naked eye. Now those same components are just a few nanometers across. That’s a billion times smaller!

Smaller transistors switch faster, use less energy and, through pure economy of scale, are cheaper to make. The jump to our latest technology node — which, by the way, is the most advanced in the world today — is no different. It offers major improvements in performance, power-efficiency and manufacturing cost.

Imagine if cars had improved at the same rate. They’d be capable of going from 0 to 60 miles per hour in a blink of an eye and circumnavigating the globe on a few drops of fuel.

Now, making chips is, to put it mildly, complicated. It takes more than a thousand separate process and measurement steps — all of which must be virtually perfect — to make a modern chip. Those steps are performed on machines, known as tools, made by hundreds of specialized companies, using ultra-pure materials, in enormous cleanrooms where the air has fewer particles in it than in the air on the moon.

Because of this complexity, the industry tends to follow a similar cadence from node to node. We call each of these “nodes” and refer to them by the smallest feature on the chip. For example, at the beginning of this millennium, we were at the 180-nanometer (nm) node. About ten years ago, we were at the 22nm node.

But a funny thing happened a few years ago in the memory world. We stopped talking about exact numbers and started to use terms like 1x, 1y and 1z. For DRAM particularly, the name of the node usually corresponds to the dimension of half of the pitch — the “half-pitch” — of the active area in the memory cell array. As for 1α, you can think of it as the fourth generation of the 10nm class where the half-pitch ranges from 10 to 19nm. As we go from 1x nanometer to 1y, 1z and 1α, this dimension gets smaller and smaller. We started with 1x, but as we continued to shrink and name the next nodes, we hit the end of the roman alphabet. That’s why we switched to the Greek alphabet alpha, beta, gamma and so on.

Putting the size into perspective

Just how small are we talking here?

Chips are fabricated, hundreds at a time, on 300mm diameter wafers of silicon. Each chip, or “die” is about the size of a fingernail.

Now imagine one die, blown up to the size of a football field. Reach down and pull out one blade of grass. Snip it in half, in half and in half again.

That's one transistor, one bit of storage out of 8 billion on a typical memory chip.

Limitations to lithography

Amazing though this is, the semiconductor industry has been doing this kind of thing, shrinking devices every year or two, for decades. We’re pretty good at it. Indeed, we know how to lay down films of material just one atom thick, and our ability to etch — selectively remove — material isn’t that far behind. So, what’s different now?

Perhaps the most difficult challenge is defining the circuit patterns on the wafer. The first part of this is called photolithography (writing on stone with light!). It’s similar to the predigital photography process, where light is shone through a small, transparent version of the photograph onto light-sensitive paper. In our case we’re shining deep ultraviolet light through a pattern laid down on a transparent square of quartz called a photomask, using a bus-sized machine. But the principle is the same.

The problem is one of physics. Thanks to something called the Rayleigh criterion, or the diffraction limit, it’s supposed to be impossible to project the image of a feature less than about half the wavelength of the light being used. It’s just not possible to create a sharp enough beam of light to make accurate patterns. In our case, the wavelength is 193nm, so we’re working way below the diffraction limit. Simplified to the point where physicists will twitch involuntarily, it’s like trying to write 10-point text using a 4-inch paintbrush.

There is a new kind of litho tool that uses smaller, 13.5nm wavelength extreme ultraviolet light (EUV), but for a number of complicated reasons, we don’t think it’s ready for prime time. Among the reasons is that the wavelength is so short that the light doesn’t pass through glass, so conventional optical lenses don’t work. Fifteen years ago, people thought EUV litho would be ready for the 32nm node. EUV’s time will come, but it’s not the right solution for 1α at Micron.

Cheating the Rayleigh criterion

We use a number of techniques to get around the diffraction limit. The first is to modify the patterns on the photomask to “fool” the light into making sharp, small features. The current state of the art is called computational lithography and uses an immense amount of processing power to effectively reverse-engineer the mask pattern from the desired pattern on the wafer.

The second is to take advantage of the fact that water diffracts light less than air and to expose the wafer underwater! This is less dramatic than it sounds. We actually replace the usual air gap between the final lens and the wafer surface with a drop of water. This approach gets us below 40nm — a great improvement and the culmination of a huge cooperative engineering effort, but not all the way home.

The magic of multiple patterning

The solution to resolution is to add a series of non-lithography steps to magically turn one “big” feature into first two and then four features, each a quarter of the size of the original. This is, frankly, brilliant. Lots of different methods to do this were worked on concurrently, but it would be remiss of me not to point out that Micron was the first to develop flash memory using double-patterning, back in 2007, thanks to the pioneering work of our own Gurtej Singh Sandhu, now a senior fellow (one of only four; it’s an exclusive club) in Micron’s pathfinding group.

Oversimplifying quite a bit, the basic idea is to create sacrificial features using the stepper, coat the sides of those features with a different material and then remove the original sacrificial features. Voilà — two half-size features! Repeat the process and we have four features of the size we need for 1α. See the diagram for more detail.

Quad patterning process flow (Image: Lam Research)

Rinse and repeat

Now we know we can accurately pattern the tiny features we need, but we’re still a long way from one complete die, let alone high-volume production. We’ve just made the outline of features for one layer, and there are dozens of layers in each chip. One thing we’re very proud of is how precisely we can align each new layer to the one before, which we call overlay. Getting that exactly right is key to making the whole thing work.

Then we have to turn the pattern into functional circuit devices such as the transistors that control reading and writing data and the tall, skinny capacitors that can store the charge representing 1’s and 0’s. This process means precisely controlling material composition and the mechanical and electrical properties of those materials, and doing it exactly the same every time.

We’re incorporating not only our own innovations but harnessing advancements from our vendor partners. We’re incorporating the latest and greatest everywhere: new materials (such as better conductors and better insulators) and new machinery to deposit, modify or selectively remove, or etch, those materials. The list is long, and all those things have to work together.

We’ve developed out fabrication plants, called fabs, into artificial intelligence-driven, highly automated marvels. As I mentioned earlier, it takes well over a thousand steps and hundreds of miles within the fab to make a modern chip. And every one of those steps must be perfect.

Semiconductor fabrication isn’t like making a car. You can’t go back and fix a defect introduced earlier in the process. Any defects are literally buried under later layers. The key to success is data — and insight from that data. Data from hundreds of thousands of sensors pours into our 10-petabyte manufacturing execution system. We feed more than a million images every day through our inspection systems and use deep learning to spot problems before they happen. Chip fabrication is perhaps the most complicated human undertaking on the planet.

How did we do it?

It’s worth asking how Micron’s engineering teams were able to pull the 1α node off, and in record time, to put us at the forefront of the industry. Micron has tens of thousands of engineers and scientists, but that’s just part of the story.

It’s a testament to the spirit of collaboration among all the disciplines involved, from our technology development, design, and product and test engineering folks to manufacturing and quality. It’s also a testament to our team members’ passion and tenacity to operate in perpetual “all hands on deck” mode to put Micron at the forefront of DRAM technology.

I’m proud of this team — and certainly proud to be a part of this team.

 

Thy Tran

Thy Tran is vice president of DRAM Process Integration in the Micron Technology Group.
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